1. Field of the Invention
The present invention relates to a method of generating a layout of a semiconductor integrated circuit by compacting hierarchical cells of the circuit and by connecting terminals of the cells to one another without wiring breaks.
2. Description of the Prior Art
A semiconductor integrated circuit has many terminals that are connected to one another according to routing techniques. Well-known routing techniques are channel routing, maze routing, line search routing, and river routing. These are explained in, for example, "Algorithms for VLSI Physical Design Automation," Naveed A. Sherwani, Kluwer Academic Publishers, 1993.
The channel routing minimizes the width of a channel sandwiched between two cell arrays, to minimize the number of tracks in a horizontal direction. The maze routing divides a chip into a lattice and generates routes on the lattice. The line search routing extends horizontal and vertical segments from start and end points and finds routs according to the segments. The river routing will be explained later.
An example of a technique for compacting a hierarchical layout of a semiconductor integrated circuit is a flat compaction. This technique develops the hierarchy into a flat form and compacts the flat form. The technique has a limit in a processible circuit scale because the processing capacity of an EWS serving as a compactor is limited to about 10,000 transistors. To solve this problem, techniques for compacting a hierarchical structure as it is have been proposed.
Such techniques include a bottom-up method and a pitch matching method. The bottom-up method compacts hierarchical cells of a given circuit from the bottom to the top. This method rewires a higher cell to a lower cell according to one of the routing techniques, in particular, the river routing technique, which wires terminals to one another in a single layer without intersections. The pitch matching method matches the pitches of terminals of cells with each other and connects the cells to each other while compacting them. The pitch matching method needs no rewiring.
Japanese Unexamined Patent Publication No. 6-58469 proposes a compromise of the bottom-up and pitch matching methods. Like the bottom-up method, the disclosure compacts hierarchical cells of a circuit sequentially from the bottom to the top. When compacting a given cell, the disclosure sets compaction constraints to restrict the movements of terminals of the cell connected to a higher cell. This makes the routing of the higher cell to the lower cell easier, like the pitch matching method.
The disclosure needs a router tool or a routing routine to connect terminals of adjacent cells to each other. In addition, the disclosure must manually connect breaks, if any. The disclosure, therefore, is troublesome for the user.
The bottom-up method has the same problem as the above disclosure because it must rewire a higher cell to a lower cell. Since the bottom-up method never adjusts the size of a lower cell, it needs a wiring area to deteriorate compaction effect.
On the other hand, the pitch matching method adjusts the pitches of terminals of hierarchical cells, to cancel the bad effect of a wiring area between cells. The pitches, however, are adjustable only when the cells are regularly arranged. If they are irregular, compaction will be stopped to provide no layout. Accordingly, the pitch matching method has limited applications. In addition, the method needs a long processing time, and therefore, is impractical.